BCM8152 ? 10 gbps transceiver with 10g cloc k, bus skew, and limiting amplifier BCM8152 functional block diagram ? 10-gigabit msa/xfp (multi-source agreement) compatible fully integrated multirate cdr, demux, cmu, and mux 16-bit lvds interface 10-gigabit serial transmitter clock output limiting amplifier on-chip pll-based clock generator line and system loopback modes receiver and transmitter serial data polarity invert bit order reversal analog loss-of-signal output (alosb) tx and rx lock detect 10-word fifo with overflow alarm absorbs system clock jitter reference clock: 1/16 or 1/64 of the selectable data rate selectable rx clock and rx data squelch selectable loop timing mode internal phase detector and charge pump for cleanup pll, external vcxo required input threshold offset adjustment and phase adjustment to optimize bit error rate and jitter tolerance margin power supplies: core, lvpecl, lvds output, and cml at 1.8v, lvds input and cmos i/o at 1.8 or 3.3v power dissipation: 1.2w typical provides compliance optical internetworking forum (oif), telcordia, itu-t, and ieee 802.3ae standards. reduces design cycle and time to market. high level of integration allows for higher port density solutions. uses the most effective silicon economy of scale for cmos- based devices. standard cmos fabrication process. features summary of benefits oc-192/stm-64/10 ge/fec transmission equipment sonet/sdh/10ge/10fc/fec optical modules add/drop multiplexers digital cross-connects atm switch backbone sonet/sdh/10ge/10fc/fec test equipment terabit and edge routers applications network interface processor network interface processor BCM8152 BCM8152 16 16 16 16 otx orx otx orx
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2004 by broadcom corporation. all rights reserved. 8152-pb03-r 02/22/05 broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are trademarks of broadcom corporation and/or its affiliates in the united states, eu and/or certain other countries. any other trademarks or trade names mentioned are the property of their respective owners. the BCM8152 is a fully integrated msa-compatible multirate sonet/ sdh/10ge/10fc/fec transceiver operating at oc-192/stm-64 (9.953 gbps), 10ge (10.3125 gbps), 10gfc (10.519 gbps), or one of four fec (forward error correction) (10.664/10.709, 11.096, or 11.31 gbps) data rates with serializer, deserializer, integrated clock multiplication unit (cmu), 10g clock, bus skew, limiting amplifier, data recovery circuit (cdr), and enhanced feature set. on-chip clock synthesis is performed by the high-frequency, low-jitter phase-locked loop (pll) on the BCM8152 transceiver chip allowing the use of a low-frequency reference clock selectable to the line rate divided by either 16 or 64. clock recovery is performed on the device by synchronizing its on-chip voltage-controlled oscillator (vco) directly to the incoming data stream. an on-chip phase detector and charge pump plus external vcxo implements a cleanup pll. the cleanup pll can be used to clean up the cdr recovered clock for loop timing applications or to clean up a noisy system clock. the low-jitter lvds interface guarantees compliance with the bit error rate requirements of the telcordia, ansi, itu-t, and ieee 802.3ae standards. the BCM8152 is packaged in a 15 x 15 mm, 301-pin bga. c b fifo control write pointer read pointer 16 x 10 fifo output retimer 16:1 mux txfifoerrb rb_tx tsdp tsdn tsclkp tsclkn pdtsclk por txresetb txpiclksel skew1/0 txpolsel txlsbsel txdin[15:0]p txdin[15:0]n txpiclkp txpiclkn rb_lvdsin multi-rate cmu txpclkn txlockerrb txmclkp txmclkp txpclkp txratesel1/0 ifsel vcp/vcn_cmu txrefsel txrefclkn txrefclkp c input register 16 b parallel lvds inputs cml serial input txmclksel rxmutepoclkb rxmutemclkb rxdout[15:0]p rxdout[15:0]n rxpoclkp rxpoclkn rxmclkp rxmclkn alosb vcp/vcn_cdr register rdinn rdinp th_alosb2/1 parallel lv ds rb_alosb rb_lvdsout rxmutedoutb alos detect cml limiting 1:16 demux multi-rate cdr output rxlsbsel rxpolsel amplifier a rxratesel1/0 rxrefsel rxlckrefb losib rxlockerrb a a a rxmclksel outputs serial input rxrefclkp rxrefclkn 16 rxrefckenb offsetp/n enextofst rxphsadj[2:0,fine]
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